-- Dekoder
-- Wejscie danych: INSTRUCTION[7..0]
-- Wyjscia:
-- INSTR(1..0) (rodzaj instrukcji)
-- ADRARG1(1..0) (tryb adresowania pierwszego argumentu)
-- ADRARG2(1..0) (tryb adresowania drugiego argumentu)
-- ARG1(3..0) (argument 1 / adres w pamieci)
-- ARG2(3..0) (argument 2 / adres w pamieci)
-- Wejscia sterujace:
-- DECODE# (dekodowanie)

library IEEE;
use IEEE.Std_Logic_1164.all;
use work.constants.all;

entity DECODER1 is
  generic (delay : time := 5 ns);
  port (DECODE                  : in std_logic;
        INSTRUCTION             : in std_logic_vector(7 downto 0);
        INSTR, ADRARG1, ADRARG2 : out std_logic_vector(1 downto 0);
        ARG1, ARG2              : out std_logic_vector(3 downto 0));
end entity DECODER1;

architecture DECODER1_arch of DECODER1 is
begin
  process(DECODE)
  begin
    if (falling_edge(DECODE)) then
      case INSTRUCTION(7 downto 4) is
        when "0000" => 
          INSTR <= CMP after delay;
          ADRARG1 <= PRZ after delay;
          ADRARG2 <= NAT after delay;
        when "0101" =>
          INSTR <= MOV after delay;
          ADRARG1 <= PRZ after delay;
          ADRARG2 <= NAT after delay;
        when others =>
          INSTR <= "ZZ";
          ADRARG1 <= "ZZ";
          ADRARG2 <= "ZZ";
          ARG1 <= "ZZZZ";
          ARG2 <= "ZZZZ";
      end case;
      ARG1 <= INSTRUCTION(3 downto 0) after delay;
    end if;
  end process;
end architecture DECODER1_arch;
